1. Field of the Invention
The present invention relates to a testing apparatus and a testing method for detecting manufacturing failure of an integrated circuit such as an LSI (Large Scale Integration) or the like, and relates to an integrated circuit having the testing apparatus.
2. Description of the Related art
Detection of manufacturing failure of, for example, an LSI is performed by applying an appropriate signal value to an input pin of the LSI using a tester, and comparing a signal value appearing at an output pin with an expected result. The signal value applied to the input pin and the expected value that should appear at the output pin are collectively called a test pattern, in general.
Defect occurring in an LSI due to manufacturing failure of the LSI is called fault. In order to verify all faults that may occur inside the LSI, a lot of test patterns are necessary. A ratio of the number of faults that can be verified with a certain pattern to the number of all faults estimated inside the LSI is called a detection ratio (or fault coverage), used as a scale when quality of the test pattern is considered. When the LSI contains a sequential circuit element [flip-flop (F/F), latch, or RAM], complexity of creation of the test pattern remarkably increases.
For this, scan design is generally made for LSIs. In an LSI applied the scan design, a shift register (called a Scan Path) is configured with sequential circuit elements (mainly F/Fs) inside the LSI, a desired value is shifted-in the shift registers at the time of test, and a value of the shift register is read out after a clock is applied.
In such a circuit, Deterministic Stored Pattern Test (hereinafter referred as DSPT) is widely employed. DSPT is performed by storing a test pattern created by Automatic Test Pattern Generator (hereinafter referred as ATPG) in a tester (ATE; Automatic Test Equipment).
FIG. 21 is a diagram for illustrating a known scan design. In FIG. 21, concept of the scan design is shown as a block diagram. As shown in FIG. 21, a plurality of scan paths (shift registers) #0, #1, . . . , and #n−1 that are routes for testing an LSI are formed in an LSI applied the scan design. Each of the scan paths #i (i=0, 1, . . . , and n−1) is configured with a plurality of F/Fs that are storage elements. A test pattern is shifted-in from one end (left side in FIG. 21) of each of the scan paths #i, and a result of the test is outputted from the other end (right side in FIG. 21).
With increase of integration of LSIs, the number of sequential circuit elements contained inside is increased. For this, when setting and reading of all sequential circuit elements configuring scan paths are repeated for each test pattern, not only the testing time is increased, but also a memory capacity of the tester becomes insufficient due to an increase of test data.
In generating a test pattern by an ATPG, a compressing method called dynamic compaction is generally used in order to decrease a quantity of test data.
The dynamic compaction is a compressing process for test data as follows: Namely, when a test for primary fault on a target is successful with a test pattern generated by an ATPG, one secondary fault is selected in a set of remaining undetected faults under net state conditions set in order to detect the primary fault, and a new value is set to a net that is still an indeterminate value to execute generation of a test pattern for the above secondary fault. A process similar to the above is repeated until another secondary fault is not selected from the set of undetected faults. When another secondary fault is selected, the same fault is not again selected. The dynamic compaction is to decrease test data by increasing the number of faults detected in units of test as above.
Even when test data is compressed in the dynamic compaction, the increase of sequential circuit elements with increase of integration of a recent LSI is extremely great. Therefore, it is difficult to solve the problems of increase of the testing time and shortage of the memory capacity of a tester.
In order to solve the above problems, Built In Self Test (hereinafter referred as BIST) is performed recently. In BIST, a pattern generated by a pseudo random pattern generator is applied to an internal circuit of an LSI, and an outputted result from the internal circuit is verified and stored by an output verifier. As the pseudo random pattern generator and the output verifier, there is used a linear feedback shift register (hereinafter referred as LFSR) is used in many cases. Particularly, the output verifier is called a multiple input signature register (hereinafter referred as MISR) since it compresses and stores outputted results as signature.
FIG. 22 is a diagram for illustrating a known BIST circuit. In FIG. 22, a concept of the BIST circuit is shown as a block diagram. As shown in FIG. 22, an LFSR 2, a phase shifter 3, a space compactor 6 and an MISR 7 along with the above scan paths #0, #1, . . . , and #n−1 are build in an LSI having the BIST circuit.
A pseudo random pattern generated by the LFSR 2 is inputted to the lead F/F of each scan path #i through the phase shifter 3. Each of outputted results from the scan path #i is compressed into about the number of bits (for example, 32 bits) of the MISR 7 by the space compactor 6, then the results are further compressed and stored by the MISR 7.
Since the LFSR (pseudo random pattern generator) 2 is mounted inside the LSI in BIST, an enormous number of test patterns can be generated within a short time, as above. The MISR 7 compresses and stores results of the test, so that a quantity of data to be loaded in the tester can be greatly decreased.
In the test on LSIs, either DSPT based on the scan design or BIST where a test circuit is built in is used now.
DSPT enables a test of a very high quality (detection ratio) since it uses test patterns created by an ATPG, thus can readily add test patterns. However, the number of test patterns is largely increased for a large scale LSI, it thus becomes difficult to store all test patterns created by the ATPG on the memory of a tester, and the testing time by the tester is increased. Therefore, a very expensive tester is required to carry out DSPT.
BIST can solve the problems of the above DSPT, but has some problems. Since pseudo random patterns are used in BIST, a quality of the test is in question. In order to increase the fault coverage, it is necessary to apply DSPT as an additional test, or insert such a test point in the internal circuit as to increase controllability and observability. MISR is used to compress data in BIST. However, even once an indeterminate state is captured, all registers in the MISR are brought into the indeterminate state, and the test cannot be carried out.
Since sequential circuit elements including a RAM inside an LSI are generally in the indeterminate state when the power source is turned on, it is necessary to beforehand apply a pattern to initialize these sequential circuit elements, or to such invent the circuit as to prevent the indeterminate state from propagating to the MISR. Other than this, the designer is forced such limitations in design too severe to apply BIST to an actual circuit that a conflict or a float state caused by the random pattern has to be prevented in design of bus and the like. Additionally, inserting the BIST circuit and a test point causes area overhead of the circuit.